The integrated circuit (IC) design is more challenging when semiconductor technologies are continually progressing to smaller feature sizes, such as 32 nanometers, 28 nanometers, 20 nanometers, and below. The performance of a designed circuit is seriously influenced by the imaging of various circuit patterns, such as doped wells, source and drains, gate electrodes, vias/contacts and other circuit features. When advanced circuit design has three dimensional structures with fin-like active regions, it is more difficult to form circuit features with proper shapes and sizes. To enhance the imaging effect when a design pattern is transferred to a wafer, optical proximity correction (OPC) is indispensable. The design pattern is adjusted to generate an image on the wafer with improved printability. However, the final wafer result is associated with various processes and factors. The lithography printing capability is limited by resist blur, mask diffraction, projection imaging resolution, electron beam blur of mask writing, resist, etch and/or other factors. The existing method is not effective to provide optimized wafer results in terms of circuit performance and fabrication cost. Especially, the mask diffraction is not isolated from other factors during certain steps of the simulation, such as calibration.
Therefore, what is needed is a method for mask simulation and mask making to effectively reduce patterning errors and address the above issues.